In the processing and packaging of semiconductor devices, wire bonding continues to be a primary method of providing electrical interconnection between two locations within a package (e.g., between a die pad of a semiconductor die and a lead of a leadframe). More specifically, using a wire bonder (also known as a wire bonding machine) wire loops are formed between respective locations to be electrically interconnected. For example, wire loops may be formed using a ball bonding machine, a wedge bonding machine, a ribbon bonding machine, etc. Exemplary wire loops formed on a ball bonding machine include (i) a ball bond bonded to a first bonding location (e.g., a die pad of a semiconductor die), (ii) a stitch bond bonded to a second bonding location (e.g., a lead of a leadframe), and (iii) a length of wire between the ball bond and the stitch bond. Exemplary patent documents related to the wire bonding industry include: U.S. Pat. Nos. 8,302,840; 9,496,240; and U.S. Patent Application Publication No. 2001/0072406—wherein each of these patent documents is incorporated by reference in its entirety.
In packages having a high number of wire loops (e.g., high pin-count wire bond applications) wire loops may be overlapping in space (e.g., crisscrossing one another in three dimensional space). The process of on-bonder looping optimization is laborious, and often involves a time period of weeks or months. Further, after the looping optimization is complete, there is no guarantee that all of the wire loops intended to be included in a given package are truly possible. The uncertainty around the feasibility of wire looping forces package designers to consider alternate packaging techniques (other than wire bonding).
Thus, it would be desirable to provide improved methods of generating loop profiles for wire loops in a semiconductor package.